Novel method of frequency synthesis for fast switching

ABSTRACT

A digital frequency synthesizer can be implemented with single source design, a multiplexer design, a fractional divider design, or a frequency multiplier and frequency divider design. Implementations can utilize a controller dithering circuit or a delta-sigma modulator. The frequency synthesizer can be implemented in a CMOS structure and can utilize a clean up phase locked loop (PLL).

CROSS-REFERENCE TO RELATED PATENT APPLICATIONS

The present application claims the benefit of and priority to and is aDivisional of U.S. application Serial No. 12/334,359, filed on Dec. 12,2008, entitled “A NOVEL METHOD OF FREQUENCY SYNTHESIS FOR FASTSWITCHING” by Sridharan, which is a Continuation of U.S. applicationSerial No. 11/321,110, filed on Dec. 29, 2005, entitled “A Novel Methodof Frequency Synthesis for Fast Switching” by Sridharan, bothapplications are incorporated herein by reference in its entirety.

BACKGROUND OF THE INVENTION

The present application generally relates to communication circuits andsystems and more specifically to frequency synthesizers using a novelopen-loop generation method. More particularly, the present applicationrelates to frequency synthesizers capable of fast switching, frequencysynthesizers capable of providing precise, high frequency clockreferences, and/or frequency synthesizers for use in communicationequipment.

According to one particular application, radio frequency (RF) signalgeneration in mobile communication equipment, frequency synthesizers areutilized to provide a frequency source for a number of communicationchannels. In general, conventional frequency synthesizers have employedinteger or fractional phase locked loops (PLLs) to generate a frequencysignal. These conventional frequency synthesizers (PLL-based frequencysynthesizers) utilize a phase locked loop comprised of a loop filter, acomparator circuit, and a voltage controlled oscillator. Theseconventional PLL-based frequency synthesizers also have used dithering,and delta-sigma dithering methods to generate the fractionalfrequencies.

The oscillator has a control input coupled to the loop filter. Theoutput of the comparator circuit is coupled to the loop filter. A firstinput of the comparator circuit is coupled to an integer divider and adelta-sigma averaging circuit. A second input of the comparator circuitis coupled to a reference signal. The combination of the integer dividerand the delta-sigma averaging circuit constitute a fractional divider.The reference frequency signal can be generated from a crystal or otherdevice. A delta-sigma fractional synthesizer is disclosed in U.S. Pat.No. 4,609,881 issued to Wells on Sep. 2, 1986.

Generally, such PLL-based frequency synthesizers are disadvantageousbecause they cannot be readily integrated on digital integrated circuits(ICs or chips). PLL-based frequency synthesizers require more expensiveprocess technologies and are not compatible with the same CMOStechnology that is used for base band and other digital controlcircuitry. As process technologies shrink in size, it becomes even moredesirous to provide a radio architecture which is compatible with CMOSprocesses. U.S. Patent Publication No. 2004/0066240 discusses certainadvantages of migrating to digitally intensive synthesizerarchitectures.

In communication applications, the frequency synthesizer must often becapable of producing precise, high frequency clock references.Heretofore, most conventional synthesizers have utilized analogintensive designs to achieve precise, high frequency clock references.These conventional analog designs cannot take advantage of the digitalprocessing capability inherent in advanced CMOS logic devices.

Therefore, there is a need for a frequency synthesizer that is morecompatible with digital designs. Further still, there is a need for asynthesizer that does not utilize a conventional PLL-based design.Further still, there is a need to integrate frequency synthesizers intoCMOS logic devices. Further still, there is a need for a frequencysynthesizer capable of fast switching which does not have thetraditional problems associated with analog-intensive designs. Yetfurther still, there is a need for a digital frequency synthesizercapable of producing precise high frequency clock signals.

SUMMARY OF THE INVENTION

An exemplary embodiment relates to a digital frequency synthesizer. Thedigital frequency synthesizer includes a frequency multiplier coupled toat least one source for providing a digital frequency signal. Thefrequency multiplier is configured to receive the digital frequencysignal at a second multiplier input and to provide a multiplier output.A delta signal modulator is configured to receive a fractional input andto provide a modulator output. The modulator output is a sequence ofintegers whose average represents the fractional input. The delta signalmodulator includes a clock input for receiving a clock signal. The clocksignal is the multiplier output signal or is derived from the multiplieroutput signal. A summer circuit is configured to receive the modulatoroutput from the delta signal modulator and an integer input and toprovide a summer output. The summer output is provided as the secondmultiplier input to the frequency multiplier.

Another exemplary embodiment relates to a frequency synthesizer. Thefrequency synthesizer includes an operator receiving a first signal at afirst operator input and a sum signal at a second operator input. Theoperator provides an output signal at a first output. The operator is adivider or a multiplier. A summer receives a modulator signal at a firstinput and an integer signal at a second input and provides the sumsignal at a summer output. The modulator provides the modulator signaland receives a fraction signal at a fraction input.

Still another exemplary embodiment relates to a frequency synthesizerincluding an operator receiving a sum signal and a clock signal andproviding an output signal and a control circuit providing a firstsignal in response to a fraction signal. A summer provides the sumsignal in response to the first signal in the frequency input.

BRIEF DESCRIPTION OF THE DRAWINGS

Preferred exemplary embodiment will hereinafter be described inconjunction with the appended drawings, wherein like numerals denotelike elements and:

FIG. 1 is an electrical schematic block diagram of a digital frequencysynthesizer in accordance with an exemplary embodiment;

FIG. 2 is a more detailed block diagram of the controller illustrated inFIG. 1 in accordance with another exemplary embodiment;

FIG. 3 is a waveform diagram of two waveforms associated with thesynthesizer illustrated in FIG. 1 in accordance with an exemplaryembodiment;

FIG. 4 is a waveform diagram of two waveforms associated with thesynthesizer illustrated in FIG. 1 in accordance with yet anotherexemplary embodiment;

FIG. 5 is an electrical schematic block diagram of a digital frequencysynthesizer in accordance with yet another exemplary embodiment;

FIG. 6 is an electrical schematic block diagram of a frequencysynthesizer in accordance with still another exemplary embodiment;

FIG. 7 is an electrical schematic block diagram of a frequencysynthesizer and a PLL circuit for cleaning output signals provided bythe frequency synthesizers illustrated in any of FIG. 1, 4, or 5 inaccordance with still yet another exemplary embodiment; and

FIG. 8 is an electrical schematic block diagram of a digital frequencysynthesizer in accordance with an exemplary embodiment.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

With reference to FIG. 1, a digital frequency synthesizer 10 can beutilized in any application requiring the generation of a frequencysignal, such as, a high frequency signal. Preferably, frequencysynthesizer 10 is a non-phase locked loop (PLL) based synthesizer thatcan be utilized in communication applications, such as, wirelesscommunication applications (e.g., cellular phone applications).Synthesizer 10 includes a number of frequency sources 12A-D, acontroller 16, and switches 14A-D. In one embodiment, synthesizer 10 isused for modulation (e.g., wideband modulation). An exemplary embodimentrelates to a digital frequency synthesizer. The digital frequencysynthesizer includes at least one source for providing a plurality ofdigital frequency signals, a plurality of switches, and a controlcircuit. Each of the digital frequency signals is provided at a distinctfrequency. The switches are coupled to receive the digital frequencysignals. The control circuit is coupled to the switches and controls theswitches to select the digital frequency signals to provide an outputsignal.

According to one embodiment, the output frequency is the average of thedigital frequency sources—as determined by a dithering sequence. Forexample, if Tone 1 is 890 MHz and Tone 2 is 900 MHz, and if thedithering sequence is Tonel, Tone2, Tonel, Tone2 . . . , then the outputfrequency is 895 MHz. As another example, if the dithering sequence isTonel, Tonel, Tonel, Tone2,...., then the output frequency is 892.5 MHz.Thus, the dithering sequence and the tone frequencies determine thefinal output frequency. This dithering sequence can be performed by acontrol circuit embodied as a sigma delta modulator, or any otherdithering sequence generator. An exemplary structure for a ditheringsequence generator is in U.S. Pat. No. 4,609,881.

Another exemplary embodiment relates to a digital frequency synthesizer.The digital frequency synthesizer includes a frequency multiplier, adelta-sigma or other dithering circuit, and a fractional input. Thefrequency multiplier has a clock input, a second input, and a multiplieroutput. The multiplier receives a clock signal at the clock input andprovides a frequency signal at the multiplier output that is the inputclock frequency times the multiplication number as set by the secondinput. The delta-sigma or other dithering circuit has a dithering outputthat provides a signal representing an “integer+fraction” for thedesired multiplication. The delta-sigma/dithering output is coupled tothe second input. The fractional input is coupled to the delta-sigma orother dithering circuit input. The fractional input provides an inputsignal that represents the fraction factor by which one wants the inputclock frequency to be multiplied.

Still another exemplary embodiment relates to a digital frequencysynthesizer. The digital frequency synthesizer includes a frequencysource for providing a first signal at a first frequency, a frequencymultiplier for receiving the first signal and providing a second signalat a second frequency, and a variable frequency divider. The digitalfrequency synthesizer also includes a delta-sigma modulator or any otherdithering circuit. The second frequency is at a fixed multiple of thefirst frequency. The frequency divider receives the second signal andprovides a third signal having an average third frequency. The averagethird frequency is less than the second frequency. The delta- sigmamodulator or other dithering circuit controls the divider so that thethird frequency is the average of a dithering sequence from thedithering circuit.

An exemplary embodiment relates to a signal source. The signal sourceincludes a digital frequency synthesizer for providing a frequencysignal and a phase lock loop clean-up circuit. The phase lock loopclean-up circuit is coupled to receive the frequency signal and providea clean-up frequency signal. The digital frequency synthesizer canutilize: 1. at least one digital frequency source, switches and adithering control circuit controlling the switches; 2. a frequencymultiplier and a dithering circuit coupled to the multiplier to providean output signal at a frequency related to an integer plus a fraction;3. a single digital frequency source capable of providing a sequence offrequency signals at distinct frequencies; or 4. a frequency multipleand variable frequency divider.

Another exemplary embodiment relates to a digital frequency synthesizerincluding at least one digital frequency source for providing aplurality of digital frequency signals and a control circuit. Thedigital frequency signals are provided at distinct frequencies. Thecontrol circuit controls the digital frequency source to provide anoutput signal having an average frequency at a first frequency. Theaverage frequency being within a range of the distinct frequencies.

Preferably, sources 12A-D and switches 14A-D are in a one-to-onerelationship. The number of sources 12A-D can be any number from two ton, and the number of switches 14A-D can be any number from two to n.Preferably, at least 2 number of sources 12A-D and switches 14A-D areutilized depending upon application parameters and system criteria.Switches 14A-D are preferably solid-state switches such as CMOS devices.Switches 14A-D can also be implemented as a multiplexer.

Frequency sources 12A-D have outputs coupled to each of switches 14A-D.Switches 14A-D have an output coupled to output 18 which is coupled tocontroller 16. Controller 16 has an output coupled to a control input ofeach of switches 14A-D via control lines 14A-D.

Sources 12A-D can be implemented as any type of frequency sources suchas integer or fractional PLLs, Clock multipliers, or multiplying DLLs.In one preferred embodiment, sources 12A-D are digital delay lockedloops (DLLS). Digital delay locked loops can be implemented asconventional DLLs.

In one alternative embodiment, frequency sources 12A-D are implementedby one delay locked loop with a programmable multiplier. This is apreferred implementation since one can recognize from FIG. 1 that when aparticular switch is on, all the other switches are off. As an example,if switch 14A connected to source 12A is on, then switches 14B, 14C, 14Dare all off. This means that the sources 12B, 12C, and 12D need not beon. Thus, the amount of hardware in the implementation may be reducedconsiderably by implementing a single frequency agile source which cangenerate signals associated with sources 12A, 12B, 12C, 12D as neededand as determined by the switches 14A to 14D.

In an alternative embodiment (FIG. 8), frequency synthesizer 500includes, a single frequency source structure 502 (e.g., single source),such as, a multiplying DLL (integer or fractional). Source 502 providesthe signals associated with sources 12A-D. In this embodiment, switches14A-D are not necessary. A controller 526, similar to controller 16described in more detail below can be utilized to cause structure 502 ofsynthesizer 500 to provide the appropriate sequence of signals. Thesequence of signals preferably have an average frequency within therange of the signals provided by source 502. Controller 526 can receivea fraction value at input 528.

In operation, frequency sources 12A-D advantageously provide a set of nprecise frequency signals. The desired frequency for a signal at output18 is somewhere within the set of n precise frequencies. The desiredfrequency is variable and can change to any frequency within the set ofn precise frequencies. For example, the desired frequency can be 905 MHzand frequencies from sources 12A-D can be 890 MHz , 900 MHz, 910 MHz,and 920 MHz, respectively. As another example, if the desired frequencyis 905 MHz, then the set of sources of 902 MHz, 904 MHz, 906 MHz, 908MHz with the appropriate dithering between them will also result in 905MHz.

The advantage of placing the tones closer to each other is that theresulting output phase noise, or jitter is considerably reduced. Thetones can be spaced equally apart from neighboring tones in oneembodiment. In another embodiment, the tones are not spaced apartequally from neighboring tones.

Controller 16 preferably controls individual switches of switches 14A-Dover time so that the output signal with the desired frequency isprovided at output 18. Controller 16 can receive a fraction factor froma fraction input 15. The fraction factor is used by controller 16 tocontrol switches 14A-D to obtain the desired frequency. Controller 16advantageously chooses the appropriate combination of frequency sources12A-D over time via control lines 14A-D so that the desired frequency isobtained. Preferably, synthesizer 10 operates as essentially a variableclock signal source which jitters around the desired frequency as shownin FIGS. 3 and 4.

Synthesizer 10 can be a frequency synthesizer for use in a cellularphone. Synthesizer 10 advantageously allows very fast switching betweenfrequencies and avoids the disadvantages associated with feedback loops.The rate of switching between switches 14A-D can be at a relatively lowrate, e.g., at crystal frequency. Alternatively, output 18 can becoupled to controller 16 as in FIG. 1 to provide a much higher switchingrate. Applicants believe that a faster switching rate for controller 16and hence switches 14A-D results in a reduced noise floor. A frequencydivider can be disposed between the output 18 and the controller 16 inorder to reduce the rate at which controller 16 operates.

Fraction input 23 provides controller 16 the appropriate fraction forproviding the desired frequency at output 18. Input 23 is similar toinput 15 (FIG. 1). The fraction can be provided by a variety ofcircuits, controllers, etc. Controller 16 generates the appropriatesequence on outputs 20A, 20B, 20C, and 20D to achieve the frequencyassociated with the fraction (e.g., integer+fraction) provided byfraction input 23. Advantageously, synthesizer 10 can have a very highbandwidth due to the lack of the feedback loop.

Synthesizer 10 can operate as an open loop system without the use offeedback loops as in a standard PLL implementation. Synthesizer 10preferably operates as a completely digital frequency source and iscapable of being integrated in an all digital CMOS process. This featurein addition to the relatively small die size required for synthesizer 10makes it very attractive for digital and analog integration.

With reference to FIG. 2, according to one preferred embodiment,controller 16 is implemented as a delta-sigma modulator or otherdithering circuit. The delta-sigma modulator receives an indication ofthe desired frequency and provides a sequence of signals on controllines 14A-D to effect generation of the desired frequency signal.

An exemplary implementation of the delta-sigma modulator is in U.S. Pat.No. 4,609,881. The output of the delta-sigma modulator (or any ditheringcircuit) is a sequence of numbers that change at the clock rate. Theinput of the delta-sigma modulator (or any dithering circuit) is afraction—for example, 0.3333. The property of the delta-sigma modulator(or any dithering circuit) is that the average of the sequence will bethe input fraction. Note that the output is preferably integer numbers.Frequency dividers or multipliers generally can be made only as integerdividers or multipliers. In the example of the input being 0.3333, theoutput sequence can be 0, 2, -1, 1, 0, 0, -2, 3, 0, and so on. Note thatthe average of the sequence is 0.3333. Another property of the delta-sigma modulator is that the sequence repeats only after a very longperiod. Thus, we obtain a pseudo-random source and the jitter or noiseat the output will not have spurious tones (since these spurious tonesare caused by any periodic repetition in the dithering sequence).

Controller 16 can be implemented as a delta-sigma modulator usingstandard architecture implemented on a CMOS process. Applicants believethat synthesizer 10 advantageously splits up the two functionsassociated with the conventional fractional-N PLL circuit (the twofunctions are that of tone generation, and noise filtering). Thearchitecture for synthesizer 10 uses digital implementation forfrequency selection and uses a PLL for filtering of the output signal.This can also be viewed as a jitter removal circuit or clean-up PLL.This clean-up PLL may not be required in all applications. Applicantsbelieve that only applications with very stringent phase noiserequirements will require the clean-up PLL. Clean-up phase locked loop34 is discussed with reference to FIG. 7. This division of two functionsassociated with a conventional PLL-base synthesizer advantageouslyreduces the power requirements and allows the use of digital circuitryfor frequency synthesizer 10.

With reference to FIG. 3, synthesizer 10 provides an output signal 202.Output signal 202 can be frequency averaged to provide output signal206, if necessary for the specific application. The averaging of thefrequency of the signal 202 can be performed utilizing a clean up phaselocked loop such as clean up phase locked loop 348 discussed withreference to FIG. 7.

Signal 202 is generated by selecting frequency sources 12A-D. As can beseen in the example, signal 202 has 8 pulses across the same time thatsignal 206 has 8 pulses. However, the pulses of signal 202 do not havethe same period between them.

Signal 202 has pulse widths (or, equivalently, pulse frequency) that canbe switched at each pulse. In this embodiment, the frequency of signal202 can be changed on a pulse-by-pulse basis. Alternatively, controller16 can control switches 14A-D at every nth pulse of the output clock.

With reference to FIG. 4, signal 208 represents the signal at output 18.Signal 208 is provided in a synthesizer 10 configured so that controller16 only selects switches 14A-D every 5 pulses, as an example. Signal 210is an average or cleaned up version of signal 208 using phase lockedloop 348 (FIG. 7).

With reference to FIG. 5, a digital frequency synthesizer 300 is similarto digital frequency synthesizer 10 and achieves similar advantages.Synthesizer 300 can be utilized to generate signals 202 and 208.

Synthesizer 300 includes a clock frequency multiplier 306, a ditheringcircuit (e.g., delta-sigma modulator 302), and a fractional input 304.Multiplier 306 receives a reference signal (CLK) at an input. Thereference signal can be provided from any frequency source, such as aDLL, crystal oscillator circuit, etc. Multiplier 306 also includes aninput for receiving a signal from a dithering circuit or (e.g.,delta-sigma modulator 302). Dithering circuit or modulator 302 providesa signal to multiplier 306 through sum circuit 307. Sum circuit 307receives an integer from integer input 309.

Sum circuit 307 adds the integer from input 309 to the fractional valuefrom modulator 302. The integer is a suitable stable integer number sothat the desired frequency output signal is provided at its output. Inthis implementation, the dithering circuit or delta sigma modulator 302provides a sequence of integer numbers whose average represents thefraction provided by input 304. Each number in the sequence is added tothe integer number which is then fed as input the clock frequencymultiplier 306.

Multiplier 306 preferably functions in the following way: the outputfrequency is a multiple of the input clock frequency. The multiple isdetermined by the second input of the multiplier 306. For example, ifthe clock frequency is 7 MHz and the multiplication number is 100, thenthe output frequency is 7*100=700 MHz. If this number keeps on varyingfor each output pulse (or at a slower rate, but still related to theoutput pulse), then synthesizer 300 is able to generate the signals 202or 208. Dithering/delta-sigma modulator circuits are discussed in moredetail above with reference to FIG. 2.

Dithering circuit or delta-sigma modulator 302 can be clocked by theoutput signal from multiplier 306 or via an external clock signal. Afraction input 304 provides the appropriate fractional input fordelta-sigma modulator 302.

With reference to FIG. 6, a frequency synthesizer 318 is similar tosynthesizer 10 and can achieve similar advantages. Synthesizer 318includes a frequency source 322, such as a crystal oscillator circuit.Synthesizer 318 also includes a frequency multiplier 326, a ditheringcircuit or delta-sigma modulator 320, a fractional input 321 and afrequency divider (or counter) 328. Synthesizer 318 also can include aninteger input 329 and a sum circuit 327. Divider 328 provides an outputsignal at a desired frequency. Dithering circuit (e.g., delta-sigmamodulator 320) is coupled to divider 328 through sum circuit 327. Sumcircuit adds the fractional output from modulator 320 to the integerfrom input 329.

Dithering circuit/delta-sigma modulator 320 controls divider 328 so thatdivider 328 provides the output signal at the desired frequency.Preferably, multiplier 326 is an integer multiplier. For example, if therequired output frequency is 900 MHz, then in one implementation, themultiplier 326 preferably multiplies the signal from crystal 322 to avery high frequency such as approximately 9 GHz.

Divider 328 divides the signal down to a desired frequency such as 905MHz. This is accomplished by dithering (or delta-sigma modulating) thedivider input so that the desired frequency and jitter is present at theoutput. The functionality is very similar to synthesizer 300 (describedabove), except for the fact that a clock multiplier is used to generatethe signals 202 or 208, while in synthesizer 318, a frequency divider isused to generate signals 202 or 208.

In one embodiment, multiplier 326 is a fixed multiplier and divider 328is a variable divider controlled by a dithering circuit (e.g.,delta-sigma modulator 320). Modulator 320 receives a signal to set thedivision for divider 328 from circuit 321.

With reference to FIG. 7, digital frequency synthesizer 352 can becoupled to clean-up synthesizer or phase locked loop 348. This clean-upsynthesizer may be required to remove the jitter inherently present insynthesizers 10, 300, or 318. Synthesizer 352 can be implemented as anyof synthesizers 10, 300 or 318. Synthesizer 352 provides a signal tophase locked loop 348. Phase locked loop 348 is a clean up phase lockedloop for removing jitter and changing waveform 202 to 206 or 208 to 210.(FIGS. 3 and 4).

Phase locked loop 348 includes a Phase detector/Phase-frequencydetector, or mixer 360, a voltage controller oscillator 362, a loopfilter 361 and an integer divider 350. The use of integer divider 350 asopposed to a fractional divider provides easier implementation. Notethat the integer division may be a division of 1. For this case, nophysical circuit is needed since the input and output frequencies arethe same. For systems, like Global System for Mobile Communications(GSM) where phase noise or jitter requirements are very difficult toachieve, loop 348 can be very advantageous. Other systems may notrequire loop 348. This separation of functions (filtering and fractionalsignal generation) allows digital implementation integrated in CMOS.

Applicants believe that the architecture of synthesizers 10, 300 and 318allows them to be made much less expensively than a conventional PLLsystem. Applicants believe that synthesizers 10, 300 or 318 have lowerpower consumption than a conventional PLL and are completely digital andmore resistant to switching noise. Modulation can be very effectivelyperformed since the method is effectively open looped and there arefewer loop stability considerations. Applicants believe that synthesizer10 provides better phase noise or jitter performance. Applicants believethat synthesizer 300 and 318 provide easier implementation at a reducedpower consumption.

It is understood that, while the detailed drawings, specific examples,and particular component values given describe preferred exemplaryembodiments of the present invention, they serve the purpose ofillustration only. The apparatus and method of the invention is notlimited to the precise details and conditions disclosed. Further,although particular types of frequency sources are discussed, variousother components could be utilized for the digital frequencysynthesizer. Other substitutions, modifications, changes, and omissionsmay be made in the design, operating conditions, and arrangement of thepreferred embodiments without departing from the spirit of the inventionas expressed in the appended claims.

1. A digital frequency synthesizer, comprising: a frequency multipliercoupled to at least one source for providing a digital frequency signal,wherein the frequency multiplier is configured to receive the digitalfrequency signal and a second multiplier input and to provide amultiplier output; a delta sigma modulator configured to receive afractional input and to provide a modulator output, wherein themodulator output is a sequence of integers whose average represents thefractional input, wherein the delta sigma modulator includes a clockinput for receiving a clock signal, wherein the clock signal is themultiplier output signal or is derived from the multiplier outputsignal; and a summer circuit configured to receive the modulator outputfrom the delta sigma modulator and an integer input and to provide asummer output, wherein the summer output is provided as the secondmultiplier input to the frequency multiplier.
 2. The digital frequencysynthesizer of claim 1, wherein the sequence of integers whose averagerepresents the fractional input are all added to the integer input togenerate the summer output.
 3. The digital frequency synthesizer ofclaim 1, wherein the digital synthesizer is utilized in a wirelesscommunication device.
 4. The digital frequency synthesizer of claim 1,wherein wideband modulation is obtained.
 5. The digital frequencysynthesizer of claim 1, wherein the multiplier output signal is providedto a clean-up phase locked loop.
 6. The digital frequency synthesizer ofclaim 1, wherein the digital frequency synthesizer is entirelyintegrated on at least one of a CMOS, bi-CMOS, silicon germanium,gallium arsenide device.
 7. A frequency synthesizer, comprising: anoperator receiving a first signal at a first operator input and a sumsignal at a second operator input and providing an output signal at afirst output, wherein the operator is a divider or multiplier; a summerreceiving a modulator signal at a first input and an integer signal at asecond summer input and providing the sum signal at a summer output; anda modulator providing the modulator signal and receiving a fractionsignal at a fraction input.
 8. The frequency synthesizer of claim 7,wherein the modulator is a delta- sigma modulator.
 9. The frequencysynthesizer of claim 7, wherein wideband modulation is obtained.
 10. Thefrequency synthesizer of claim 7, further comprising: providing theoutput signal to a clean-up phase locked loop.
 11. The frequencysynthesizer of claim 7, wherein the operator is a multiplier and theoutput signal is coupled to a clock input of the modulator.
 12. Thefrequency synthesizer of claim 11, wherein the modulator is adelta-sigma modulator.
 13. The frequency synthesizer of claim 7, whereinthe operator is a divider.
 14. The digital frequency synthesizer ofclaim 13, wherein a multiplier is coupled to the first input.
 15. Adigital frequency synthesizer, comprising: an operator receiving a sumsignal and a clock signal and providing an output signal; a controlcircuit providing a first signal in response to a fraction signal; and asummer providing the sum signal in response to the first signal andfrequency input.
 16. The digital frequency synthesizer of claim 15,wherein the control circuit includes a dithering circuit.
 17. Thedigital frequency synthesizer of claim 16, wherein the control comprisesa delta-sigma modulator.
 18. The digital frequency synthesizer of claim17, wherein wideband modulation is achieved.
 19. The digital frequencysynthesizer of claim 15, wherein the operator is a multiplier.
 20. Thedigital frequency synthesizer of claim 15, wherein output signal isprovided as a clock input to the control circuit.